Re: [PATCH 1/1] iommu/vt-d: Fix missed device TLB cache tag

[Vasant Hegde]

Jason,


On 6/20/2024 7:38 PM, Jason Gunthorpe wrote:
> On Thu, Jun 20, 2024 at 04:19:46PM +0530, Vasant Hegde wrote:
>>>>>> seems that for all domain attaches above is coded in a wrong order
>>>>>> as ats is enabled after the cache tag is assigned.
>>>>> Yes, exactly. But simply changing the order isn't future-proof,
>>>>> considering ATS control will eventually be moved out of iommu drivers.
>>>> [Unrelated to this patch]
>>>>
>>>> You mean ATS setup will be moved to individual device driver? Is there any
>>>> reason for that?
>>>
>>> Not exactly to individual device drivers, but it should be out of the
>>> iommu drivers.
>>>
>>> https://lore.kernel.org/linux-iommu/BL1PR12MB51441FC4303BD0442EDB7A9CF7FFA@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx/
>>
>> Got it. Thanks.
>>
>> I remember of this discussion. May be we can provide API from IOMMU driver so
>> that individual driver can enable/disable ATS (like iommu_dev_enable_feature()).
> 
> But I have a feeling if we do that it should be done by re-attaching
> the domain.

Right. By default IOMMU will enable the ATS.. But if device driver decides to
disable it (say due to HW bug), then we have to re-attach domain (in AMD case we
have to update the DTE and flush the TLB).


> 
> For instance if you look at how I structued SMMUv3, the ATSness is an
> effective property of the domain type and ATS switches on and off
> dynamically already.

In AMD case its per device property. We check both IOMMU capability and device
property before enabling ATS.

> 
> Having an additional input to domain attach "inhibit ats", as a flag
> would be all the support the driver would need to provide for the core
> code to manage this with some kind of global policy.

You mean for attach_dev() ?

.. and what about PRI and PASID? Don't device driver needs similar interface ?


-Vasant