Re: [PATCH] arm64: Cleanup __cpu_set_tcr_t0sz()

[Catalin Marinas]

On Thu, 23 May 2024 21:21:46 +0900, Seongsu Park wrote:
> The T0SZ field of TCR_EL1 occupies bits 0-5 of the register and encode
> the virtual address space translated by TTBR0_EL1. When updating the
> field, for example because we are switching to/from the idmap page-table,
> __cpu_set_tcr_t0sz() erroneously treats its 't0sz' argument as unshifted,
> resulting in harmless but confusing double shifts by 0 in the code.
> 
> 
> [...]

Applied to arm64 (for-next/misc), thanks!

[1/1] arm64: Cleanup __cpu_set_tcr_t0sz()
      https://git.kernel.org/arm64/c/cf938f91784f

-- 
Catalin