Re: [PATCH v2 07/12] i2c: riic: Define individual arrays to describe the register offsets

[Geert Uytterhoeven]

Hi Biju,

On Fri, Jun 28, 2024 at 10:09 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > -----Original Message-----
> > From: claudiu beznea <claudiu.beznea@xxxxxxxxx>
> > On 28.06.2024 10:55, Biju Das wrote:
> > > Are we sure RZ/A does not support fast mode plus?
> >
> > From commit description of patch 09/12:
> >
> > Fast mode plus is available on most of the IP variants that RIIC driver is working with. The
> > exception is (according to HW manuals of the SoCs where this IP is available) the Renesas RZ/A1H.
> > For this, patch introduces the struct riic_of_data::fast_mode_plus.
> >
> > I checked the manuals of all the SoCs where this driver is used.
> >
> > I haven't checked the H/W manual?
> >
> > On the manual I've downloaded from Renesas web site the FMPE bit of RIICnFER is not available on
> > RZ/A1H.
>
> I just found RZ/A2M manual, it supports FMP and register layout looks similar to RZ/G2L.
> Wolfram tested it with r7s72100 genmai board acessing an eeprom. Not sure is it RZ/A1 or RZ/A2?

Genmai is RZ/A1H (r7s72100).

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

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