Re: [PATCH v5] PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)

[Krzysztof Wilczyński]

Hello,

> Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0
> (SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an
> inbound PCIe TLP spans more than two internal AXI 128-byte bursts,
> the bus may corrupt the packet payload and the corrupt data may
> cause associated applications or the processor to hang.
> 
> The workaround for Errata #i2037 is to limit the maximum read
> request size and maximum payload size to 128 bytes. Add workaround
> for Errata #i2037 here. The errata and workaround is applicable
> only to AM65x SR 1.0 and later versions of the silicon will have
> this fixed.
> 
> [1] -> https://www.ti.com/lit/er/sprz452i/sprz452i.pdf

Jan, thank you for picking up this patch.  Siddharth, thank you for being
very thorough, chasing after old review comments to be addressed.

Much appreciated on both accounts!

	Krzysztof