Re: [PATCH v2 02/10] dt-bindings: riscv: Add SpacemiT X60 compatibles

[Conor Dooley]

On Thu, Jun 27, 2024 at 03:31:16PM +0000, Yixun Lan wrote:
> From: Yangyu Chen <cyy@xxxxxxxxxxxx>
> 
> The X60 is RISC-V CPU cores from SpacemiT and currently used in their K1
> SoC.
> 
> Link: https://www.spacemit.com/en/spacemit-x60-core/
> 

Same comment as v1 here :) With that addressed,
Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>

Thanks,
Conor.

> Signed-off-by: Yangyu Chen <cyy@xxxxxxxxxxxx>
> Signed-off-by: Yixun Lan <dlan@xxxxxxxxxx>
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index d87dd50f1a4b5..5ad9cb4103356 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -46,6 +46,7 @@ properties:
>                - sifive,u7
>                - sifive,u74
>                - sifive,u74-mc
> +              - spacemit,x60
>                - thead,c906
>                - thead,c910
>                - thead,c920
> 
> -- 
> 2.45.2
>

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