On Tue 02 Jul 2024 at 15:34, George Stark <gnstark@xxxxxxxxxxxxxxxxx> wrote:
The chip has 3 dual-channel PWM modules PWM_AB, PWM_CD, PWM_EF.
Signed-off-by: George Stark <gnstark@xxxxxxxxxxxxxxxxx>
Signed-off-by: Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxxxxx>
---
.../devicetree/bindings/pwm/pwm-amlogic.yaml | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
index 1d71d4f8f328..e021cf59421a 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
+++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
The change is not only introducing a1 compatibility but also allowing a
power-domain for the other SoC, even if optional.
If that is intended, it should be stated in the description and probably
a separate change.
"#pwm-cells":
const: 3
@@ -136,6 +143,16 @@ allOf:
required:
- clocks
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,meson-a1-pwm
+ then:
+ required:
+ - power-domains
+
additionalProperties: false
examples: