On 05/07/2024 04:15, Chris Packham wrote:
The timer/counter block on the Realtek SoCs provides up to 5 timers. It
also includes a watchdog timer which is handled by the
realtek_otto_wdt.c driver.
One timer will be used per CPU as a local clock event generator. An
additional timer will be used as an overal stable clocksource.
Does the mips arch have a local timer per cpu timer and a broadcast timer already integrated in the GIC ?