[PATCH v2 0/2] iommu/vt-d: Fix aligned pages for cache invalidation

[Lu Baolu]

The aligned pages for cache invalidation returned by
calculate_psi_aligned_address() are incorrect if the start pfn is not
aligned, which can lead to cache inconsistencies when qi_flush_piotlb()
uses the number of pages to flush caches for the first-stage
translation.

Fix this by updating the aligned pages once the address mask is adjusted.

Change log:

v2:
 - Add a new fix to Limit max address mask to MAX_AGAW_PFN_WIDTH.

v1: https://lore.kernel.org/linux-iommu/20240708121417.18705-1-baolu.lu@xxxxxxxxxxxxxxx/

Lu Baolu (2):
  iommu/vt-d: Limit max address mask to MAX_AGAW_PFN_WIDTH
  iommu/vt-d: Fix aligned pages in calculate_psi_aligned_address()

 drivers/iommu/intel/cache.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

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2.34.1