Re: [PATCH v2 06/10] riscv: Implement xchg8/16() using Zabha
From: Guo Ren
Date: Tue Jul 09 2024 - 21:37:45 EST
On Wed, Jun 26, 2024 at 9:10 PM Alexandre Ghiti <alexghiti@xxxxxxxxxxxx> wrote:
>
> This adds runtime support for Zabha in xchg8/16() operations.
>
> Signed-off-by: Alexandre Ghiti <alexghiti@xxxxxxxxxxxx>
> ---
> arch/riscv/include/asm/cmpxchg.h | 33 +++++++++++++++++++++++++++++---
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/kernel/cpufeature.c | 1 +
> 3 files changed, 32 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
> index da42f32ea53d..eb35e2d30a97 100644
> --- a/arch/riscv/include/asm/cmpxchg.h
> +++ b/arch/riscv/include/asm/cmpxchg.h
> @@ -11,8 +11,17 @@
> #include <asm/fence.h>
> #include <asm/alternative.h>
>
> -#define __arch_xchg_masked(sc_sfx, prepend, append, r, p, n) \
> +#define __arch_xchg_masked(sc_sfx, swap_sfx, prepend, sc_append, \
> + swap_append, r, p, n) \
> ({ \
> + __label__ zabha, end; \
> + \
> + if (IS_ENABLED(CONFIG_RISCV_ISA_ZABHA)) { \
> + asm goto(ALTERNATIVE("nop", "j %[zabha]", 0, \
> + RISCV_ISA_EXT_ZABHA, 1) \
> + : : : : zabha); \
> + } \
> + \
Could we exchange the sequence between Zabha & lr/sc?
I mean:
nop -> zabha
j -> lr/sc
> u32 *__ptr32b = (u32 *)((ulong)(p) & ~0x3); \
> ulong __s = ((ulong)(p) & (0x4 - sizeof(*p))) * BITS_PER_BYTE; \
> ulong __mask = GENMASK(((sizeof(*p)) * BITS_PER_BYTE) - 1, 0) \
> @@ -28,12 +37,25 @@
> " or %1, %1, %z3\n" \
> " sc.w" sc_sfx " %1, %1, %2\n" \
> " bnez %1, 0b\n" \
> - append \
> + sc_append \
> : "=&r" (__retx), "=&r" (__rc), "+A" (*(__ptr32b)) \
> : "rJ" (__newx), "rJ" (~__mask) \
> : "memory"); \
> \
> r = (__typeof__(*(p)))((__retx & __mask) >> __s); \
> + goto end; \
> + \
> +zabha:
jump lr/sc implementation because it's already slow.
\
> + if (IS_ENABLED(CONFIG_RISCV_ISA_ZABHA)) { \
> + __asm__ __volatile__ ( \
> + prepend \
> + " amoswap" swap_sfx " %0, %z2, %1\n" \
> + swap_append \
> + : "=&r" (r), "+A" (*(p)) \
> + : "rJ" (n) \
> + : "memory"); \
> + } \
> +end:; \
> })
>
> #define __arch_xchg(sfx, prepend, append, r, p, n) \
> @@ -56,8 +78,13 @@
> \
> switch (sizeof(*__ptr)) { \
> case 1: \
> + __arch_xchg_masked(sc_sfx, ".b" swap_sfx, \
> + prepend, sc_append, swap_append, \
> + __ret, __ptr, __new); \
> + break; \
> case 2: \
> - __arch_xchg_masked(sc_sfx, prepend, sc_append, \
> + __arch_xchg_masked(sc_sfx, ".h" swap_sfx, \
> + prepend, sc_append, swap_append, \
> __ret, __ptr, __new); \
> break; \
> case 4: \
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index e17d0078a651..f71ddd2ca163 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -81,6 +81,7 @@
> #define RISCV_ISA_EXT_ZTSO 72
> #define RISCV_ISA_EXT_ZACAS 73
> #define RISCV_ISA_EXT_XANDESPMU 74
> +#define RISCV_ISA_EXT_ZABHA 75
>
> #define RISCV_ISA_EXT_XLINUXENVCFG 127
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 5ef48cb20ee1..c125d82c894b 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -257,6 +257,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
> __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
> __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
> + __RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA),
> __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
> __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
> __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
> --
> 2.39.2
>
--
Best Regards
Guo Ren