Re: [PATCH 6/6] PCI: align small (<4k) BARs

[Ilpo Järvinen]

On Tue, 9 Jul 2024, Stewart Hildebrand wrote:

> Issues observed when small (<4k) BARs are not 4k aligned are:
> 
> 1. Devices to be passed through (to e.g. a Xen HVM guest) with small
> (<4k) BARs require each memory BAR to be page aligned. Currently, the
> only way to guarantee this alignment from a user perspective is to fake
> the size of the BARs using the pci=resource_alignment= option. This is a
> bad user experience, and faking the BAR size is not always desirable.
> See the comment in drivers/pci/pci.c:pci_request_resource_alignment()
> for further discussion.
> 
> 2. Devices with multiple small (<4k) BARs could have the MSI-X tables
> located in one of its small (<4k) BARs. This may lead to the MSI-X
> tables being mapped in the same 4k region as other data. The PCIe 6.1
> specification (section 7.7.2 MSI-X Capability and Table Structure) says
> we probably shouldn't do that.
> 
> To improve the user experience, and increase conformance to PCIe spec,
> set the default minimum resource alignment of memory BARs to 4k. Choose
> 4k (rather than PAGE_SIZE) for the alignment value in the common code,
> since that is the value called out in the PCIe 6.1 spec, section 7.7.2.
> The new default alignment may be overridden by arches by implementing
> pcibios_default_alignment(), or by the user with the
> pci=resource_alignment= option.
> 
> Signed-off-by: Stewart Hildebrand <stewart.hildebrand@xxxxxxx>
> ---
> Preparatory patches in this series are prerequisites to this patch.
> ---
>  drivers/pci/pci.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 9f7894538334..e7b648304383 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -6453,7 +6453,12 @@ struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
>  
>  resource_size_t __weak pcibios_default_alignment(void)
>  {
> -	return 0;
> +	/*
> +	 * Avoid MSI-X tables being mapped in the same 4k region as other data
> +	 * according to PCIe 6.1 specification section 7.7.2 MSI-X Capability
> +	 * and Table Structure.
> +	 */
> +	return 4 * 1024;

SZ_4K

+ add #include for it if its not yet included by the .c file.

-- 
 i.