Re: [PATCH v10 4/9] spi: cadence: Add Marvell SDMA operations

[Mark Brown]

On Tue, Jul 09, 2024 at 03:12:06PM -0700, Witold Sadowski wrote:
> In Marvell xSPI implementation any access to SDMA register will result
> in 8 byte SPI data transfer. Reading less data(eg. 1B) will result in
> losing remaining bytes. To avoid that read/write 8 bytes into temporary
> buffer, and read/write whole temporary buffer into SDMA.

This breaks an x86 allmodconfig build:

/build/stage/linux/drivers/spi/spi-cadence-xspi.c: In function ‘m_ioreadq’:
/build/stage/linux/drivers/spi/spi-cadence-xspi.c:524:17: error: implicit declar
ation of function ‘ioread64_rep’; did you mean ‘ioread32_rep’? [-Werror=implicit
-function-declaration]
  524 |                 ioread64_rep(addr, buf, full_ops);
      |                 ^~~~~~~~~~~~
      |                 ioread32_rep
/build/stage/linux/drivers/spi/spi-cadence-xspi.c: In function ‘m_iowriteq’:
/build/stage/linux/drivers/spi/spi-cadence-xspi.c:544:17: error: implicit declar
ation of function ‘iowrite64_rep’; did you mean ‘iowrite32_rep’? [-Werror=implic
it-function-declaration]
  544 |                 iowrite64_rep(addr, buf, full_ops);
      |                 ^~~~~~~~~~~~~
      |                 iowrite32_rep
cc1: all warnings being treated as errors

(and there were some issues from 0day, didn't check if they were the
same.)

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