Re: [PATCH 1/2] arm64: dts: ti: k3-j784s4-evm: Assign only lanes 0 and 1 to PCIe1

[Siddharth Vadapalli]

On Wed, Jul 10, 2024 at 10:36:13AM -0500, Andrew Halaney wrote:
> Currently PCIe1 is setup to use SERDES0 lanes 0 thru 3, and USB0 is
> setup to use SERDES0 lane 3 as well.
> 
> This overlap in lanes causes the following reset related lane splat:
> 
>     [    4.846266] WARNING: CPU: 4 PID: 308 at drivers/reset/core.c:792 __reset_control_get_internal+0x128/0x160
>     ...
>     [    4.846405] Call trace:
>     [    4.846407]  __reset_control_get_internal+0x128/0x160
>     [    4.846413]  __of_reset_control_get+0x4e0/0x528
>     [    4.846418]  of_reset_control_array_get+0xa4/0x1f8
>     [    4.846423]  cdns_torrent_phy_probe+0xbc8/0x1068 [phy_cadence_torrent]
>     [    4.846445]  platform_probe+0xb4/0xe8
>     ...
>     [    4.846577] cdns-torrent-phy 5060000.serdes: phy@0: failed to get reset
> 
> Let's limit the PCIe1 SERDES0 lanes to 0 and 1 to avoid overlap here.
> This works since PCIe1 operates in x2 mode and doesn't need 4 SERDES0
> lanes.
> 
> Fixes: 27ce26fe52d4 ("arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode")
> Suggested-by: Siddharth Vadapalli <s-vadapalli@xxxxxx>
> Signed-off-by: Andrew Halaney <ahalaney@xxxxxxxxxx>

Thank you for posting this patch.

Reviewed-by: Siddharth Vadapalli <s-vadapalli@xxxxxx>

Regards,
Siddharth.