Re: [PATCH 2/4] drm/bridge: add Microchip DSI controller support for sam9x7 SoC series

From: Manikandan.M
Date: Thu Jul 11 2024 - 06:08:30 EST


On 11/07/24 3:28 pm, Conor Dooley wrote:
> On Thu, Jul 11, 2024 at 11:05:37AM +0200, Krzysztof Kozlowski wrote:
>> On 11/07/2024 10:30,Manikandan.M@xxxxxxxxxxxxx wrote:
>>> Hi Krzysztof,
>>>
>>> On 04/07/24 4:27 pm, Krzysztof Kozlowski wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On 04/07/2024 10:48, Manikandan Muralidharan wrote:
>>>>> Add the Microchip's DSI controller wrapper driver that uses
>>>>> the Synopsys DesignWare MIPI DSI host controller bridge.
>>>>>
>>>>> Signed-off-by: Manikandan Muralidharan<manikandan.m@xxxxxxxxxxxxx>
>>>>> ---
>>>>
>>>> ...
>>>>
>>>>> +
>>>>> +#define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \
>>>>> +{ \
>>>>> + .maxfreq = _maxfreq, \
>>>>> + .timing = { \
>>>>> + .clk_lp2hs = _c_lp2hs, \
>>>>> + .clk_hs2lp = _c_hs2lp, \
>>>>> + .data_lp2hs = _d_lp2hs, \
>>>>> + .data_hs2lp = _d_hs2lp, \
>>>>> + } \
>>>>> +}
>>>>> +
>>>>> +struct hstt hstt_table[] = {
>>>> So more globals? No.
>>> In the sam9x7 datasheet, the high speed transition time for data and
>>> clock lane at different freq for the DSI controller ranges are tabulated
>>> with constant values.
>>> I referred other similar platforms for the functionality and found
>>> similar way of implementation, only a few had equations to derive the
>>> low power and high speed timings.I am not able to come up with a more
>>> efficient method. If there is something I am missing, please suggest.
>>> TIA
>> Yeah, this should not be a global. Nothing above suggests it.
> I think what Krzysztof is suggesting here is use of the static
> keyword...
Yes, after looking at the implementation in similar platforms, I did
find out.
Thank you Conor.
>
>> BTW, no W=1 clang warnings? Are you sure?
>>
>> Best regards,
>> Krzysztof

--
Thanks and Regards,
Manikandan M.