Hi Bryan,
On 7/11/24 2:07 PM, Bryan O'Donoghue wrote:
On 11/07/2024 12:41, Quentin Schulz wrote:
Worst case XVCLK period is 1.365 milliseconds.
If your theory on the GPIO is correct, its still difficult to see how @ 6MHz - which we don't yet support and probably never will, that 1.5 milliseconds would be insufficient.
So - I'm happy enough to throw out the first patch and give a range of 1.5 to 1.6 milliseconds instead.
Works for me.