On Thu, Jul 11, 2024 at 11:32:30AM +0200, AngeloGioacchino Del Regno wrote:
The secondary XHCI controller, using a PHY that is shared between
it and the secondary PCI-Express controller, gets powered by the
PCIE_MAC_P1 power domain.
Add this power domain to the usb@11290000 node to fix probe.
Fixes: 37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation board")
Reported-by: Nícolas F. R. A. Prado <nfraprado@xxxxxxxxxxxxx> #KernelCI
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
Hi Angelo,
thanks for the patch, but unfortunately it doesn't fix the issue:
[ 10.772128] mtk-pcie-gen3 112f8000.pcie: host bridge /soc/pcie@112f8000 ranges:
[ 10.788914] mtk-pcie-gen3 112f8000.pcie: IO 0x0024000000..0x00241fffff -> 0x0024000000
[ 10.802111] mtk-pcie-gen3 112f8000.pcie: MEM 0x0024200000..0x0027ffffff -> 0x0024200000
[ 10.941278] mtk-pcie-gen3 112f8000.pcie: PCI host bridge to bus 0000:00
[ 10.785937] xhci-mtk 11290000.usb: uwk - reg:0x400, version:104
[ 10.796352] xhci-mtk 11290000.usb: xHCI Host Controller
[ 10.810530] xhci-mtk 11290000.usb: new USB bus registered, assigned bus number 5
[ 10.844258] xhci-mtk 11290000.usb: clocks are not stable (0x1003d0f)
[ 10.844262] xhci-mtk 11290000.usb: can't setup: -110
[ 10.844266] xhci-mtk 11290000.usb: USB bus 5 deregistered
[ 10.861969] xhci-mtk 11290000.usb: probe with driver xhci-mtk failed with error -110
In fact it seems to have made the issue more frequent, as it happened every time
for the 5 boots I tried.
But that gives me idea to try booting with clk_ignore_unused and
pd_ignore_unused. I'll update the report with the results.
Thanks,
Nícolas
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 2ee45752583c..96ad1b14626e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1445,6 +1445,7 @@ xhci1: usb@11290000 {
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
phys = <&u2port1 PHY_TYPE_USB2>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
<&topckgen CLK_TOP_SSUSB_XHCI_1P>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
--
2.45.2