Re: [PATCH v3 1/2] arm64: dts: rockchip: Add sdmmc_ext for RK3328

[Dragan Simic]

Hello Diederik,

On 2024-07-10 15:28, Diederik de Haas wrote:
> From: Alex Bee <knaerzche@xxxxxxxxx>
>
> RK3328 SoC has a fourth mmc controller called SDMMC_EXT. Some
> boards have sdio wifi connected to it. In order to use it
> one would have to add the pinctrls from sdmmc0ext group which
> is done on board level.
>
> Signed-off-by: Alex Bee <knaerzche@xxxxxxxxx>
> Signed-off-by: Diederik de Haas <didi.debian@xxxxxxxxx>

Looking good to me, cross-referencing the RK3328 TRM and the downstream
RK3328 SoC dtsi checks out.  Though, it will remain inert in our 
codebase,
because no supported boards use it, but that's fine, we're still 
improving
the correctness of the RK3328 SoC dtsi.

Reviewed-by: Dragan Simic <dsimic@xxxxxxxxxxx>

> ---
>  arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> index b01efd6d042c..95c3f1303544 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> @@ -1036,6 +1036,20 @@ usb_host0_ohci: usb@ff5d0000 {
>  		status = "disabled";
>  	};
>
> +	sdmmc_ext: mmc@ff5f0000 {
> +		compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
> +		reg = <0x0 0xff5f0000 0x0 0x4000>;
> +		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
> +			 <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
> +		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> +		fifo-depth = <0x100>;
> +		max-frequency = <150000000>;
> +		resets = <&cru SRST_SDMMCEXT>;
> +		reset-names = "reset";
> +		status = "disabled";
> +	};
> +
>  	usbdrd3: usb@ff600000 {
>  		compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
>  		reg = <0x0 0xff600000 0x0 0x100000>;