Re: [PATCH V6 2/5] mailbox: Add support for QTI CPUCP mailbox controller

From: Nathan Chancellor
Date: Sun Jul 14 2024 - 23:15:05 EST


Hi Sibi,

On Wed, Jun 12, 2024 at 06:10:53PM +0530, Sibi Sankar wrote:
> Add support for CPUSS Control Processor (CPUCP) mailbox controller,
> this driver enables communication between AP and CPUCP by acting as
> a doorbell between them.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> Signed-off-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
> ---
>
> v5:
> * Fix build error reported by kernel test robot by adding 64BIT requirement
> to COMPILE_TEST
...
> +config QCOM_CPUCP_MBOX
> + tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver"
> + depends on ARCH_QCOM || (COMPILE_TEST && 64BIT)

This doesn't work, ARCH=arm allmodconfig is still broken with:

drivers/mailbox/qcom-cpucp-mbox.c: In function 'qcom_cpucp_mbox_irq_fn':
drivers/mailbox/qcom-cpucp-mbox.c:54:18: error: implicit declaration of function 'readq'; did you mean 'readb'? [-Wimplicit-function-declaration]
54 | status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT);
| ^~~~~
| readb
drivers/mailbox/qcom-cpucp-mbox.c:65:17: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Wimplicit-function-declaration]
65 | writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR);
| ^~~~~~
| writel

because there is ARCH_QCOM for that architecture as well.

You could resolve this by just including either io-64-nonatomic-hi-lo.h
or io-64-nonatomic-lo-hi.h or shuffling the dependencies to require
64BIT unconditionally:

diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index d1f6c758b5e8..8d46b76c23fd 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -278,7 +278,7 @@ config SPRD_MBOX

config QCOM_CPUCP_MBOX
tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver"
- depends on ARCH_QCOM || (COMPILE_TEST && 64BIT)
+ depends on 64BIT && (ARCH_QCOM || COMPILE_TEST)
help
Qualcomm Technologies, Inc. CPUSS Control Processor (CPUCP) mailbox
controller driver enables communication between AP and CPUCP. Say

Cheers,
Nathan