[PATCH v3 0/3] riscv: Per-thread envcfg CSR support

From: Samuel Holland
Date: Wed Jul 17 2024 - 20:56:34 EST


This series (or equivalent) is a prerequisite for both user-mode pointer
masking and CFI support, as both of those are per-thread features and
are controlled by fields in the envcfg CSR. These patches are based on
v1 of the pointer masking series[1], with significant input from both
Deepak and Andrew.

[1]: https://lore.kernel.org/linux-riscv/20240319215915.832127-6-samuel.holland@xxxxxxxxxx/

Changes in v3:
- Rebase on riscv/for-next
- Drop use of __initdata due to conflicts with cpufeature.c refactoring

Changes in v2:
- Rebase on riscv/for-next

Samuel Holland (3):
riscv: Enable cbo.zero only when all harts support Zicboz
riscv: Add support for per-thread envcfg CSR values
riscv: Call riscv_user_isa_enable() only on the boot hart

arch/riscv/include/asm/cpufeature.h | 2 +-
arch/riscv/include/asm/processor.h | 1 +
arch/riscv/include/asm/switch_to.h | 8 ++++++++
arch/riscv/kernel/cpufeature.c | 11 ++++++++---
arch/riscv/kernel/smpboot.c | 2 --
arch/riscv/kernel/suspend.c | 4 ++--
6 files changed, 20 insertions(+), 8 deletions(-)

--
2.45.1