Re: [PATCH v2 0/3] Add the core reset for UARTs of StarFive JH7110

[patchwork-bot+linux-riscv]

Hello:

This series was applied to riscv/linux.git (for-next)
by Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>:

On Tue,  4 Jun 2024 16:47:26 +0800 you wrote:
> The UART of StarFive JH7110 needs two reset signals (apb, core) to
> initialize. This patch series adds the missing core reset.
> 
> Changes since v1:
> - Set maxItems to 1 for resets from other platforms.
> 
> History:
> v1: https://lore.kernel.org/all/20240517061713.95803-1-hal.feng@xxxxxxxxxxxxxxxx/
> 
> [...]

Here is the summary with links:
  - [v2,1/3] dt-bindings: serial: snps-dw-apb-uart: Add one more reset signal for StarFive JH7110 SoC
    (no matching commit)
  - [v2,2/3] serial: 8250_dw: Use reset array API to get resets
    (no matching commit)
  - [v2,3/3] riscv: dts: starfive: jh7110: Add the core reset and jh7110 compatible for uarts
    https://git.kernel.org/riscv/c/4ed81d9dd75f

You are awesome, thank you!
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