Re: [PATCH] mailbox: qcom-cpucp: fix 64BIT dependency

[Sibi Sankar]

On 7/19/24 15:32, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@xxxxxxxx>
>
> This newly added driver fails compile testing on 32-bit architectures
> because it relies on 64-bit MMIO register access:
>
> drivers/mailbox/qcom-cpucp-mbox.c: In function 'qcom_cpucp_mbox_irq_fn':
> drivers/mailbox/qcom-cpucp-mbox.c:54:18: error: implicit declaration of function 'readq'; did you mean 'readb'? [-Wimplicit-function-declaration]
>     54 |         status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT);
>        |                  ^~~~~
>        |                  readb
> drivers/mailbox/qcom-cpucp-mbox.c:65:17: error: implicit declaration of function 'writeq'; did you mean 'writeb'? [-Wimplicit-function-declaration]
>     65 |                 writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR);
>        |                 ^~~~~~
>        |                 writeb
>
> Change the Kconfig dependency to disallow that configuration as well.
>
> Fixes: 0e2a9a03106c ("mailbox: Add support for QTI CPUCP mailbox controller")
> Signed-off-by: Arnd Bergmann <arnd@xxxxxxxx>
> ---
>   drivers/mailbox/Kconfig | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
> index d1f6c758b5e8..4eed97295927 100644
> --- a/drivers/mailbox/Kconfig
> +++ b/drivers/mailbox/Kconfig
> @@ -278,7 +278,7 @@ config SPRD_MBOX
>   
>   config QCOM_CPUCP_MBOX
>   	tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver"
> -	depends on ARCH_QCOM || (COMPILE_TEST && 64BIT)
> +	depends on (ARCH_QCOM || COMPILE_TEST) && 64BIT

Hey Arnd,

Thanks for the patch. This was first reported by Nathan [1] and I
was planning on re-posting the series after the merge window. Thanks
again.

Reviewed-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>

[1] https://lore.kernel.org/lkml/20240715031451.GA2940276@thelio-3990X/

>   	help
>   	  Qualcomm Technologies, Inc. CPUSS Control Processor (CPUCP) mailbox
>   	  controller driver enables communication between AP and CPUCP. Say