Re: [PATCH 4/5] arm64: dts: renesas: r9a07g044(l1): Correct GICD and GICR sizes

[Geert Uytterhoeven]

Hi Prabhakar,

On Thu, Jul 25, 2024 at 3:41 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> The RZ/G2L SoC is equipped with the GIC-600. The GICD + GICDA is 128kB,
> and the GICR is 128kB per CPU.
>
> Fixes: 68a45525297b2 ("arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's")
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> @@ -1043,8 +1043,8 @@ gic: interrupt-controller@11900000 {
>                         #interrupt-cells = <3>;
>                         #address-cells = <0>;
>                         interrupt-controller;
> -                       reg = <0x0 0x11900000 0 0x40000>,
> -                             <0x0 0x11940000 0 0x60000>;
> +                       reg = <0x0 0x11900000 0 0x20000>,
> +                             <0x0 0x11940000 0 0x40000>;
>                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
>                 };
>
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> index 9cf27ca9f1d2..6f4d4dc13f50 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> @@ -16,3 +16,8 @@ cpus {
>                 /delete-node/ cpu@100;
>         };
>  };
> +
> +&gic {
> +       reg = <0x0 0x11900000 0 0x20000>,
> +             <0x0 0x11940000 0 0x20000>;
> +};

What's the point of overriding this here?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds