Re: [PATCH v4 1/3] arm64: dts: rockchip: Add missing pinctrl for PCIe30x4 node

[Dragan Simic]

Hello Anand,

On 2024-07-26 13:00, Anand Moon wrote:
> Add missing pinctrl settings for PCIe 3.0 x4 clock request and wake
> signals. Each component of PCIe communication have the following 
> control
> signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to 
> generate
> high-speed signals and communicate with other PCIe devices.
> Used by root complex to endpoint depending on the power state.
>
> PERST is referred to as a fundamental reset. PERST should be held low
> until all the power rails in the system and the reference clock are 
> stable.
> A transition from low to high in this signal usually indicates the
> beginning of link initialization.
>
> WAKE signal is an active-low signal that is used to return the PCIe
> interface to an active state when in a low-power state.
>
> CLKREQ signal is also an active-low signal and is used to request the
> reference clock.
>
> Rename node from 'pcie3' to 'pcie30x4' to align with schematic
> nomenclature.

I wonder why the three patches in this series cannot be squashed into
a single patch, because they target the same thing for the same board
dts file?  I don't think that having these three separate patches may
help with possible regression tracking in the future, for example.

> Signed-off-by: Anand Moon <linux.amoon@xxxxxxxxx>
> ---
> v4: rebase on master, used RK_FUNC_GPIO GPIO function instead of PIN
> number.
> V3: use pinctrl local to board
> V2: Update the commit messge to describe the changs.
>     use pinctl group as its pre define in pinctrl dtsi
> ---
>  .../arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 18 ++++++++++++------
>  1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
> b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
> index 966bbc582d89..1c7080cca11f 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
> @@ -338,7 +338,7 @@ &pcie30phy {
>
>  &pcie3x4 {
>  	pinctrl-names = "default";
> -	pinctrl-0 = <&pcie3_rst>;
> +	pinctrl-0 = <&pcie30x4_pins>;
>  	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
>  	vpcie3v3-supply = <&vcc3v3_pcie30>;
>  	status = "okay";
> @@ -377,14 +377,20 @@ pcie2_2_rst: pcie2-2-rst {
>  		};
>  	};
>
> -	pcie3 {
> -		pcie3_rst: pcie3-rst {
> -			rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
> -		};
> -
> +	pcie30x4 {
>  		pcie3_vcc3v3_en: pcie3-vcc3v3-en {
>  			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
>  		};
> +
> +		pcie30x4_pins: pcie30x4-pins {
> +			rockchip,pins =
> +				/* PCIE30X4_CLKREQn_M1_L */
> +				<4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
> +				/* PCIE30X4_PERSTn_M1_L */
> +				<4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>,
> +				/* PCIE30X4_WAKEn_M1_L */
> +				<4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
> +		};
>  	};
>
>  	usb {
>
> base-commit: 1722389b0d863056d78287a120a1d6cadb8d4f7b