RE: [PATCH v3 1/4] dt-bindings: net: Add FSD EQoS device tree bindings

From: Swathi K S
Date: Mon Jul 29 2024 - 04:57:10 EST




> -----Original Message-----
> From: Andrew Lunn <andrew@xxxxxxx>
> Sent: 06 June 2024 18:56
> To: Swathi K S <swathi.ks@xxxxxxxxxxx>
> Cc: davem@xxxxxxxxxxxxx; edumazet@xxxxxxxxxx; kuba@xxxxxxxxxx;
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> mcoquelin.stm32@xxxxxxxxx; alim.akhtar@xxxxxxxxxxx; linux-
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> Subject: Re: [PATCH v3 1/4] dt-bindings: net: Add FSD EQoS device tree
bindings
>
> > > > + fsd-rx-clock-skew:
> > > > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > > > + items:
> > > > + - items:
> > > > + - description: phandle to the syscon node
> > > > + - description: offset of the control register
> > > > + description:
> > > > + Should be phandle/offset pair. The phandle to the syscon
node.
> > >
> > > What clock are you skew-ing here? And why?
> >
> > As per customer's requirement, we need 2ns delay in fsys block both in
> > TX and RX path.
>
> Lots of people get RGMII delays wrong. Please look back at the mailing
list
> where there is plenty of discussion about this. I don't want to have to
repeat
> myself yet again...

Sorry for the delay.
We took time to confirm with the board designer regarding this delay.
This is not a mandatory one to have and hence we are dropping clock-skewing
here.

>
> Andrew

Thanks,
Swathi