Re: [PATCH V7] LoongArch: Add AVEC irqchip support

[Thomas Gleixner]

Huacai!

On Tue, Jul 30 2024 at 16:51, Huacai Chen wrote:
> On Fri, Jul 26, 2024 at 11:12 PM Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote:
>> > +     while (true) {
>> > +             vector = csr_read64(LOONGARCH_CSR_IRR);
>> > +             if (vector & IRR_INVALID_MASK)
>> > +                     break;
>> > +
>> > +             vector &= IRR_VECTOR_MASK;
>> > +
>> > +             d = this_cpu_read(irq_map[vector]);
>> > +             if (d)
>> > +                     generic_handle_irq_desc(d);
>> > +             else {
>>
>> See bracket rules.
> Do you mean even if there is only one statement in the if condition,
> we still need to do like this?
> if (xxx) {
>     yyy;
> } else {
>     zzz;
> }

Yes. It's documented.

>> > +     msi_domain = pci_msi_create_irq_domain(pch_msi_handle[0],
>> > +                                            &pch_msi_domain_info_v2, parent);
>>
>> Please don't do that. Convert this to use per device MSI domains.
> OK, thanks. But it is better to split the conversion to another patch
> (so we can convert both V1 and V2).

Why adding it first?

This can be done per interrupt chip. See the conversion series for
ARM[64]:

    https://lore.kernel.org/r/20240623142137.448898081@xxxxxxxxxxxxx

Thanks,

        tglx