[PATCH v2 0/4] arm64: dts: renesas: Correct GICD and GICR sizes

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Hi All,

This patch series aims to correct GICD and GICR sizes on RZ/G2L(LC),
RZ/G2UL, RZ/V2L and RZ/G3S SoCs. These SoCs are equipped with GIC-600.

GIC-600 supports MBI by default, so GICD size is set to 128kB.
On RZ/G2UL and RZ/G3S SoC despite being single core the GICR size is set
to 256kB as dumping the GICR_IIDR register shows it has two instances of
GICR.

v1->v2
- Dropped changes for single core
- Updated commit message

Cheers,
Prabhakar

Lad Prabhakar (4):
  arm64: dts: renesas: r9a08g045: Correct GICD and GICR sizes
  arm64: dts: renesas: r9a07g043u: Correct GICD and GICR sizes
  arm64: dts: renesas: r9a07g054: Correct GICD and GICR sizes
  arm64: dts: renesas: r9a07g044: Correct GICD and GICR sizes

 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 4 ++--
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi  | 4 ++--
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi  | 4 ++--
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi  | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

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2.34.1