[PATCH 06/10] clk: qcom: gpucc-sm8450: Add SM8475 support

[Danila Tikhonov]

Add support to the SM8475 graphics clock controller by extending the
SM8450 graphics clock controller, which is almost identical but has
some minor differences.

Signed-off-by: Danila Tikhonov <danila@xxxxxxxxxxx>
---
 drivers/clk/qcom/Kconfig        |  3 ++-
 drivers/clk/qcom/gpucc-sm8450.c | 25 ++++++++++++++++++++++++-
 2 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 702de741cedd..eb2c8db95daf 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -1123,7 +1123,8 @@ config SM_GPUCC_8450
 	depends on ARM64 || COMPILE_TEST
 	select SM_GCC_8450
 	help
-	  Support for the graphics clock controller on SM8450 devices.
+	  Support for the graphics clock controller on SM8450 or SM8475
+	  devices.
 	  Say Y if you want to support graphics controller devices and
 	  functionality such as 3D graphics.
 
diff --git a/drivers/clk/qcom/gpucc-sm8450.c b/drivers/clk/qcom/gpucc-sm8450.c
index b3c5d6923cd2..35ebf93fdb66 100644
--- a/drivers/clk/qcom/gpucc-sm8450.c
+++ b/drivers/clk/qcom/gpucc-sm8450.c
@@ -736,6 +736,7 @@ static const struct qcom_cc_desc gpu_cc_sm8450_desc = {
 
 static const struct of_device_id gpu_cc_sm8450_match_table[] = {
 	{ .compatible = "qcom,sm8450-gpucc" },
+	{ .compatible = "qcom,sm8475-gpucc" },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, gpu_cc_sm8450_match_table);
@@ -748,6 +749,28 @@ static int gpu_cc_sm8450_probe(struct platform_device *pdev)
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
+	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-gpucc")) {
+		/* Update GPUCC PLL0 Config */
+		gpu_cc_pll0_config.config_ctl_hi1_val = 0x82aa299c;
+		gpu_cc_pll0_config.test_ctl_val = 0x00000000;
+		gpu_cc_pll0_config.test_ctl_hi_val = 0x00000003;
+		gpu_cc_pll0_config.test_ctl_hi1_val = 0x00009000;
+		gpu_cc_pll0_config.test_ctl_hi2_val = 0x00000034;
+		gpu_cc_pll0_config.user_ctl_hi_val = 0x00000005;
+
+		gpu_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+
+		/* Update GPUCC PLL1 Config */
+		gpu_cc_pll1_config.config_ctl_hi1_val = 0x82aa299c;
+		gpu_cc_pll1_config.test_ctl_val = 0x00000000;
+		gpu_cc_pll1_config.test_ctl_hi_val = 0x00000003;
+		gpu_cc_pll1_config.test_ctl_hi1_val = 0x00009000;
+		gpu_cc_pll1_config.test_ctl_hi2_val = 0x00000034;
+		gpu_cc_pll1_config.user_ctl_hi_val = 0x00000005;
+
+		gpu_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+	}
+
 	clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
 	clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
 
@@ -763,5 +786,5 @@ static struct platform_driver gpu_cc_sm8450_driver = {
 };
 module_platform_driver(gpu_cc_sm8450_driver);
 
-MODULE_DESCRIPTION("QTI GPU_CC SM8450 Driver");
+MODULE_DESCRIPTION("QTI GPU_CC SM8450 / SM8475 Driver");
 MODULE_LICENSE("GPL");
-- 
2.45.2