Re: [PATCH v4 02/13] riscv: Do not fail to build on byte/halfword operations with Zawrs

[Guo Ren]

On Thu, Aug 1, 2024 at 1:27 AM Waiman Long <longman@xxxxxxxxxx> wrote:
>
> On 7/31/24 03:23, Alexandre Ghiti wrote:
> > riscv does not have lr instructions on byte and halfword but the
> > qspinlock implementation actually uses such atomics provided by the
> > Zabha extension, so those sizes are legitimate.
>
> Note that the native qspinlock code only need halfword atomic cmpxchg
> operation. However, if you also plan to use paravirtual qspinlock, you
> need to have byte-level atomic cmpxchg().
Thx for reminding me; I will update paravirt qspinlock after these
patches merge.

Zabha & Zcas extension provides byte and half-word atomic cmpxchg.

>
> Cheers,
> Longman
>
> >
> > Then instead of failing to build, just fallback to the !Zawrs path.
> >
> > Signed-off-by: Alexandre Ghiti <alexghiti@xxxxxxxxxxxx>
> > ---
> >   arch/riscv/include/asm/cmpxchg.h | 3 ++-
> >   1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
> > index ebbce134917c..9ba497ea18a5 100644
> > --- a/arch/riscv/include/asm/cmpxchg.h
> > +++ b/arch/riscv/include/asm/cmpxchg.h
> > @@ -268,7 +268,8 @@ static __always_inline void __cmpwait(volatile void *ptr,
> >               break;
> >   #endif
> >       default:
> > -             BUILD_BUG();
> > +             /* RISC-V doesn't have lr instructions on byte and half-word. */
> > +             goto no_zawrs;
> >       }
> >
> >       return;
>


-- 
Best Regards
 Guo Ren