Re: [PATCH v5 1/5] dt-bindings: ata: Add i.MX8QM AHCI compatible string

[Frank Li]

On Fri, Aug 02, 2024 at 02:46:49PM +0800, Richard Zhu wrote:
> Add i.MX8QM AHCI "fsl,imx8qm-ahci" compatible strings.
>
> i.MX8QM AHCI SATA doesn't require AHB clock rate to set the vendor
> specified TIMER1MS register. ahb clock is not required by i.MX8QM AHCI.
>
> Update the description of clocks in the dt-binding accordingly.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>

Reviewed-by: Frank Li <Frank.Li@xxxxxxx>
> ---
>  .../devicetree/bindings/ata/imx-sata.yaml     | 47 +++++++++++++++++++
>  1 file changed, 47 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/ata/imx-sata.yaml b/Documentation/devicetree/bindings/ata/imx-sata.yaml
> index 68ffb97ddc9b2..f4eb3550a0960 100644
> --- a/Documentation/devicetree/bindings/ata/imx-sata.yaml
> +++ b/Documentation/devicetree/bindings/ata/imx-sata.yaml
> @@ -19,6 +19,7 @@ properties:
>        - fsl,imx53-ahci
>        - fsl,imx6q-ahci
>        - fsl,imx6qp-ahci
> +      - fsl,imx8qm-ahci
>
>    reg:
>      maxItems: 1
> @@ -27,12 +28,14 @@ properties:
>      maxItems: 1
>
>    clocks:
> +    minItems: 2
>      items:
>        - description: sata clock
>        - description: sata reference clock
>        - description: ahb clock
>
>    clock-names:
> +    minItems: 2
>      items:
>        - const: sata
>        - const: sata_ref
> @@ -58,6 +61,25 @@ properties:
>      $ref: /schemas/types.yaml#/definitions/flag
>      description: if present, disable spread-spectrum clocking on the SATA link.
>
> +  phys:
> +    items:
> +      - description: phandle to SATA PHY.
> +          Since "REXT" pin is only present for first lane of i.MX8QM PHY, it's
> +          calibration result will be stored, passed through second lane, and
> +          shared with all three lanes PHY. The first two lanes PHY are used as
> +          calibration PHYs, although only the third lane PHY is used by SATA.
> +      - description: phandle to the first lane PHY of i.MX8QM.
> +      - description: phandle to the second lane PHY of i.MX8QM.
> +
> +  phy-names:
> +    items:
> +      - const: sata-phy
> +      - const: cali-phy0
> +      - const: cali-phy1
> +
> +  power-domains:
> +    maxItems: 1
> +
>  required:
>    - compatible
>    - reg
> @@ -65,6 +87,31 @@ required:
>    - clocks
>    - clock-names
>
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - fsl,imx53-ahci
> +              - fsl,imx6q-ahci
> +              - fsl,imx6qp-ahci
> +    then:
> +      properties:
> +        clock-names:
> +          minItems: 3
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - fsl,imx8qm-ahci
> +    then:
> +      properties:
> +        clock-names:
> +          minItems: 2
> +
>  additionalProperties: false
>
>  examples:
> --
> 2.37.1
>