Re: [PATCH] MIPS: Loongson64: Set timer mode in cpu-probe

[Thomas Bogendoerfer]

On Tue, Jul 23, 2024 at 05:15:44PM +0800, Jiaxun Yang wrote:
> Loongson64 C and G processors have EXTIMER feature which
> is conflicting with CP0 counter.
> 
> Although the processor resets in EXTIMER disabled & INTIMER
> enabled mode, which is compatible with MIPS CP0 compare, firmware
> may attempt to enable EXTIMER and interfere CP0 compare.
> 
> Set timer mode back to MIPS compatible mode to fix booting on
> systems with such firmware before we have an actual driver for
> EXTIMER.
> 
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx>
> ---
> Please take this patch via fixes (or second 6.11 PR) tree so it can
> reach stable faster.
> 
> Thansks!
> ---
>  arch/mips/kernel/cpu-probe.c | 4 ++++
>  1 file changed, 4 insertions(+)

applied to mips-fixes.

Thomas.

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