Re: [PATCH] perf/x86/intel: Restrict period on Haswell

From: Thomas Gleixner
Date: Sat Aug 17 2024 - 08:23:22 EST


On Fri, Aug 16 2024 at 15:27, Kan Liang wrote:
> On 2024-08-15 7:43 p.m., Thomas Gleixner wrote:
>
> The HSW11 is also BDM11. It sounds like we need the trick from both bdw
> and nhm.
>
> How about this?
>
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index e8bd45556c30..42f557a128b9 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -4664,6 +4664,12 @@ static void nhm_limit_period(struct perf_event
> *event, s64 *left)
> *left = max(*left, 32LL);
> }
>
> +static void hsw_limit_period(struct perf_event *event, s64 *left)
> +{
> + nhm_limit_period(event, left);
> + bdw_limit_period(event, left);
> +}
> static void glc_limit_period(struct perf_event *event, s64 *left)
> {
> if (event->attr.precise_ip == 3)
>
> Do you plan to post the "limit" patch for HSW?
> Or should I send the patch?

Go wild...