On Wed, 21 Aug 2024 10:51:27 +0100,
Kunkun Jiang <jiangkunkun@xxxxxxxxxx> wrote:
Hi all,
Recently I discovered a problem about GICv4.1, the scenario is as follows:
1. Enable GICv4.1
2. Create multiple VMs.For example, 50 VMs(4U8G)
I don't know what 4U8G means. On how many physical CPUs are you
running 50 VMs? Direct injection of interrupts and over-subscription
are fundamentally incompatible.
3. The business running in VMs has a frequent mmio access and need to exit
to qemu for processing.
4. Or modify the kvm code so that wfi must trap to kvm
5. Then the utilization of pcpu where the vcpu is located will be 100%,and
basically all in sys.
What did you expect? If you trap all the time, your performance will
suck. Don't do that.
6. This problem does not exist in GICv3.
Because GICv3 doesn't have the same constraints.
According to analysis, this problem is due to the execution of vgic_v4_load.
vcpu_load or kvm_sched_in
kvm_arch_vcpu_load
...
vgic_v4_load
irq_set_affinity
...
irq_do_set_affinity
raw_spin_lock(&tmp_mask_lock)
chip->irq_set_affinity
...
its_vpe_set_affinity
The tmp_mask_lock is the key. This is a global lock. I don't quite
understand
why tmp_mask_lock is needed here. I think there are two possible
solutions here:
1. Remove this tmp_mask_lock
Maybe you could have a look at 33de0aa4bae98 (and 11ea68f553e24)? It
would allow you to understand the nature of the problem.
This can probably be replaced with a per-CPU cpumask, which would
avoid the locking, but potentially result in a larger memory usage.
2. Modify the gicv4 driver,do not perfrom VMOVP via
irq_set_affinity.
Sure. You could also not use KVM at all if don't care about interrupts
being delivered to your VM. We do not send a VMOVP just for fun. We
send it because your vcpu has moved to a different CPU, and the ITS
needs to know about that.
You seem to be misunderstanding the use case for GICv4: a partitioned
system, without any over-subscription, no vcpu migration between CPUs.
If that's not your setup, then GICv4 will always be a net loss
compared to SW injection with GICv3 (additional HW interaction,
doorbell interrupts).