Re: [PATCH v14 6/6] iommu/arm-smmu: add support for PRR bit setup
From: kernel test robot
Date: Thu Aug 22 2024 - 18:38:19 EST
Hi Bibek,
kernel test robot noticed the following build warnings:
[auto build test WARNING on joro-iommu/next]
[also build test WARNING on linus/master v6.11-rc4 next-20240822]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Bibek-Kumar-Patro/iommu-arm-smmu-re-enable-context-caching-in-smmu-reset-operation/20240817-014609
base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next
patch link: https://lore.kernel.org/r/20240816174259.2056829-7-quic_bibekkum%40quicinc.com
patch subject: [PATCH v14 6/6] iommu/arm-smmu: add support for PRR bit setup
config: arm-randconfig-r071-20240823 (https://download.01.org/0day-ci/archive/20240823/202408230612.1DU9cuSx-lkp@xxxxxxxxx/config)
compiler: arm-linux-gnueabi-gcc (GCC) 14.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240823/202408230612.1DU9cuSx-lkp@xxxxxxxxx/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@xxxxxxxxx>
| Closes: https://lore.kernel.org/oe-kbuild-all/202408230612.1DU9cuSx-lkp@xxxxxxxxx/
All warnings (new ones prefixed by >>):
In file included from include/linux/scatterlist.h:9,
from include/linux/iommu.h:10,
from include/linux/io-pgtable.h:6,
from include/linux/adreno-smmu-priv.h:9,
from drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:7:
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c: In function 'qcom_adreno_smmu_set_prr_addr':
>> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:266:41: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
266 | (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_LADDR);
| ^
arch/arm/include/asm/io.h:282:75: note: in definition of macro 'writel_relaxed'
282 | #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
| ^
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:269:41: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
269 | (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_UADDR);
| ^
arch/arm/include/asm/io.h:282:75: note: in definition of macro 'writel_relaxed'
282 | #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
| ^
vim +266 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
256
257 static void qcom_adreno_smmu_set_prr_addr(const void *cookie, phys_addr_t page_addr)
258 {
259 struct arm_smmu_domain *smmu_domain = (void *)cookie;
260 struct arm_smmu_device *smmu = smmu_domain->smmu;
261 const struct device_node *np = smmu->dev->of_node;
262
263 if (of_device_is_compatible(np, "qcom,smmu-500") &&
264 of_device_is_compatible(np, "qcom,adreno-smmu")) {
265 writel_relaxed(lower_32_bits(page_addr),
> 266 (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_LADDR);
267
268 writel_relaxed(upper_32_bits(page_addr),
269 (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_UADDR);
270 }
271 }
272
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