The current driver sets the response buffer threshold value to 1Reviewed-by: Jarkko Nikula <jarkko.nikula@xxxxxxxxxxxxxxx>
(N+1, 2 DWORDS) in the QUEUE THRESHOLD register. However, the AMD
I3C controller only generates interrupts when the response buffer
threshold value is set to 0 (1 DWORD).
Therefore, a quirk is added to set the response buffer threshold value
to 0.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@xxxxxxx>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@xxxxxxx>
Co-developed-by: Guruvendra Punugupati <Guruvendra.Punugupati@xxxxxxx>
Signed-off-by: Guruvendra Punugupati <Guruvendra.Punugupati@xxxxxxx>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@xxxxxxx>
---
drivers/i3c/master/mipi-i3c-hci/core.c | 6 +++++-
drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++
drivers/i3c/master/mipi-i3c-hci/hci_quirks.c | 11 +++++++++++
3 files changed, 18 insertions(+), 1 deletion(-)