Re: [PATCH v2 2/2] clk: renesas: r9a09g057-cpg: Add clock and reset entries for GTM/RIIC/SDHI/WDT

[Geert Uytterhoeven]

Hi Prabhakar,

On Thu, Aug 22, 2024 at 1:16 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Add clock and reset entries for GTM, RIIC, SDHI and WDT IP blocks.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> ---
> v1->v2
> - Updated DDIV_PACK macro to accommodate width

Thanks for the update!

> --- a/drivers/clk/renesas/rzv2h-cpg.h
> +++ b/drivers/clk/renesas/rzv2h-cpg.h
> @@ -8,6 +8,13 @@
>  #ifndef __RENESAS_RZV2H_CPG_H__
>  #define __RENESAS_RZV2H_CPG_H__
>
> +#define CPG_CDDIV0             (0x400)
> +
> +#define DDIV_PACK(offset, bitpos, mon, size) \
> +               (((mon) << 19) | ((offset) << 8) | ((bitpos) << 4) | (size))

I think the DDIV_PACK() macro (using C bitfields?) belongs in the
previous patch.

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds