Re: [RFC 0/2] irqchip/loongson-eiointc: Add multiple interrupt pin routing support

[Huacai Chen]

Hi, Jianmin,

What's your opinion on this series?

Huacai

On Wed, Aug 21, 2024 at 6:11 PM Bibo Mao <maobibo@xxxxxxxxxxx> wrote:
>
> There are four times about EIOINTC_REG_ISR register group access in
> eiointc irq handler, in order to get all irq status about 256 interrupt
> vectors. It causes four times VM-exits since eiointc register are
> software emulated, here multiple interrupt pin routing is introduced
> and each 64 interrupt vector is routed to one interrupt pin.
>
> With this method, there will be only on one EIOINTC_REG_ISR register
> group acces in irq handler, it will reduce VM-exits.
>
> Bibo Mao (2):
>   irqchip/loongson-eiointc: Route interrupt parsed from acpi table
>   irqchip/loongson-eiointc: Add multiple interrupt pin routing support
>
>  arch/loongarch/kernel/irq.c            |  3 +-
>  arch/loongarch/kernel/smp.c            |  2 +-
>  drivers/irqchip/irq-loongson-eiointc.c | 66 +++++++++++++++++++++++---
>  3 files changed, 62 insertions(+), 9 deletions(-)
>
>
> base-commit: 1fb918967b56df3262ee984175816f0acb310501
> --
> 2.39.3
>
>