Re: [PATCH v3 1/4] x86/cpufeatures: Clarify semantics of X86_FEATURE_IBPB

[Jim Mattson]

On Mon, Aug 26, 2024 at 1:33 PM Pawan Gupta
<pawan.kumar.gupta@xxxxxxxxxxxxxxx> wrote:
>
> On Fri, Aug 23, 2024 at 11:53:10AM -0700, Jim Mattson wrote:
> > Since this synthetic feature bit is set on AMD CPUs that don't flush
> > the RSB on an IBPB, indicate as much in the comment, to avoid
> > potential confusion with the Intel IBPB semantics.
> >
> > Signed-off-by: Jim Mattson <jmattson@xxxxxxxxxx>
> > ---
> >  arch/x86/include/asm/cpufeatures.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> > index dd4682857c12..cabd6b58e8ec 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -215,7 +215,7 @@
> >  #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE        ( 7*32+23) /* Disable Speculative Store Bypass. */
> >  #define X86_FEATURE_LS_CFG_SSBD              ( 7*32+24)  /* AMD SSBD implementation via LS_CFG MSR */
> >  #define X86_FEATURE_IBRS             ( 7*32+25) /* "ibrs" Indirect Branch Restricted Speculation */
> > -#define X86_FEATURE_IBPB             ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier */
> > +#define X86_FEATURE_IBPB             ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without RSB flush */
>
> I don't think the comment is accurate for Intel. Maybe you meant to modify
> X86_FEATURE_AMD_IBPB?

It's perhaps a bit terse, but this is what I meant. Perhaps better
would be "without guaranteed RSB flush"?