RE: [PATCH v7 1/2] clk: starfive: jh7110-sys: Add notifier for PLL0 clock

[Hal Feng]

> On 26.08.24 16:04, Xingyu Wu wrote:
> Add notifier function for PLL0 clock. In the function, the cpu_root clock should
> be operated by saving its current parent and setting a new safe parent (osc
> clock) before setting the PLL0 clock rate. After setting PLL0 rate, it should be
> switched back to the original parent clock.
> 
> Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>
> Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx>

Reviewed-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx>