RE: [PATCH v7 1/2] clk: starfive: jh7110-sys: Add notifier for PLL0 clock

[Xingyu Wu]

On 29/08/2024 04:19, Stephen Boyd wrote:
> 
> Quoting Xingyu Wu (2024-08-26 01:04:29)
> > Add notifier function for PLL0 clock. In the function, the cpu_root
> > clock should be operated by saving its current parent and setting a
> > new safe parent (osc clock) before setting the PLL0 clock rate. After
> > setting PLL0 rate, it should be switched back to the original parent clock.
> >
> > Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110
> > SoC")
> > Reviewed-by: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>
> > Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx>
> > ---
> 
> What is the urgency of this patch? I can't tell from the commit text, so I'm
> assuming it can bake in clk-next for a few weeks.

Hi Stephen,

This is urgent. Without this patch, Cpufreq does not work and the CPU can't work in the best frequency of 1.5GHz. This patch can improve the performance of the visionfive-2 board.

Best regards,
Xingyu Wu