RE: [PATCH net] net: xilinx: axienet: Fix IRQ coalescing packet count overflow

From: Pandey, Radhey Shyam
Date: Wed Sep 04 2024 - 13:22:57 EST


> -----Original Message-----
> From: Sean Anderson <sean.anderson@xxxxxxxxx>
> Sent: Tuesday, September 3, 2024 11:31 PM
> To: Pandey, Radhey Shyam <radhey.shyam.pandey@xxxxxxx>; David S .
> Miller <davem@xxxxxxxxxxxxx>; Eric Dumazet <edumazet@xxxxxxxxxx>;
> Jakub Kicinski <kuba@xxxxxxxxxx>; Paolo Abeni <pabeni@xxxxxxxxxx>;
> netdev@xxxxxxxxxxxxxxx
> Cc: Simek, Michal <michal.simek@xxxxxxx>; linux-arm-
> kernel@xxxxxxxxxxxxxxxxxxx; Ariane Keller <ariane.keller@xxxxxxxxxxxxxx>;
> linux-kernel@xxxxxxxxxxxxxxx; Daniel Borkmann <daniel@xxxxxxxxxxxxx>;
> Andy Chiu <andy.chiu@xxxxxxxxxx>; Sean Anderson
> <sean.anderson@xxxxxxxxx>
> Subject: [PATCH net] net: xilinx: axienet: Fix IRQ coalescing packet count
> overflow
>
> If coalesce_count is greater than 255 it will not fit in the register and
> will overflow. Clamp it to 255 for more-predictable results.
>
> Signed-off-by: Sean Anderson <sean.anderson@xxxxxxxxx>
> Fixes: 8a3b7a252dca ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet
> driver")
> ---
>
> drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> index 9aeb7b9f3ae4..5f27fc1c4375 100644
> --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> @@ -252,7 +252,8 @@ static u32 axienet_usec_to_timer(struct axienet_local
> *lp, u32 coalesce_usec)
> static void axienet_dma_start(struct axienet_local *lp)
> {
> /* Start updating the Rx channel control register */
> - lp->rx_dma_cr = (lp->coalesce_count_rx <<
> XAXIDMA_COALESCE_SHIFT) |
> + lp->rx_dma_cr = (min(lp->coalesce_count_rx, 255) <<
> + XAXIDMA_COALESCE_SHIFT) |
> XAXIDMA_IRQ_IOC_MASK |

Instead of every time clamping coalesce_count_rx on read I think better
to do it place where it set in axienet_ethtools_set_coalesce()? It would
also represent the coalesce count state that is reported by get_coalesce()
and same is being used in programming.


> XAXIDMA_IRQ_ERROR_MASK;
> /* Only set interrupt delay timer if not generating an interrupt on
> * the first RX packet. Otherwise leave at 0 to disable delay interrupt.
> @@ -264,7 +265,8 @@ static void axienet_dma_start(struct axienet_local
> *lp)
> axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr);
>
> /* Start updating the Tx channel control register */
> - lp->tx_dma_cr = (lp->coalesce_count_tx <<
> XAXIDMA_COALESCE_SHIFT) |
> + lp->tx_dma_cr = (min(lp->coalesce_count_tx, 255) <<
> + XAXIDMA_COALESCE_SHIFT) |
> XAXIDMA_IRQ_IOC_MASK |
> XAXIDMA_IRQ_ERROR_MASK;
> /* Only set interrupt delay timer if not generating an interrupt on
> * the first TX packet. Otherwise leave at 0 to disable delay interrupt.
> --
> 2.35.1.1320.gc452695387.dirty