Re: [PATCH V6 0/5] phy: freescale: fsl-samsung-hdmi: Expand phy clock options

[Frieder Schrempf]

On 05.09.24 1:30 AM, Adam Ford wrote:
> Currently, there is a look-up-table to describe all the clock options the HDMI PHY
> can use.  Some of these entries in the LUT are using a fractional divider which does
> not have a well documented algorithm for determinging values, but the the integer
> divider can use an algorithm to calculate the integer divder values dynamically
> beyond those listed in the LUT and also duplicates some of the entries.
> 
> The first two patches do not do anything functionally other than simplify
> some of the register accesses and de-duplicates some of the register look-ups.
> 
> The third patch adds support for the integer divider and uses it whenever the
> clock request is an exact match.  Otherwise, it will use the LUT as before.
> The rouding is still based on the LUT if the integer clock isn't an exact match.
> 
> The forth patch updates thes set_rate and round_rate functions to use either
> the fractional clock LUT or the the integer divder mechanism to determine
> which ever clock rate might be closest match.
> 
> The last patch removes the integer divider entries from the LUT since by then
> it'll be comparing both the integer divider calculator and the closest value
> in the LUT.
> 
> In my testing with a AOC 4K monitor, I was able to add 4 entries in my modetest
> table.  I do not have an HDMI analyzer, so I just used my monitor to determine
> if this series worked.

So I tested this series and it works fine. With Dominique's patch to
allow for 0.5% deviation for the clock, all the 24 modes of my monitor
and 30 out of 42 modes of my HDMI grabber are working now.

I still have some issues with LCDIF underrun errors on modeswitch with
v6.11-rc6 but these are unrelated to this series.

Thanks Adam and Dominique for the great work!