[PATCH 0/4] clk: meson: Fix an issue with inaccurate hifi_pll frequency

[Chuan Liu via B4 Relay]

Some PLLs with fractional multipliers have fractional denominators that
are fixed to "100000" instead of the previous "(1 << pll->frac.width)".

The hifi_pll for both C3 and S4 supports a fractional multiplier and has
a fixed fractional denominator of "100000".

Here are the results of the C3-based command tests (already defined
CLOCK_ALLOW_WRITE_DEBUGFS):
* echo 491520000 > /sys/kernel/debug/clk/hifi_pll/clk_rate
* cat /sys/kernel/debug/clk/hifi_pll/clk_rate
491520000
* echo 1 > /sys/kernel/debug/clk/hifi_pll/clk_prepare_enable
* cat /sys/kernel/debug/meson-clk-msr/clks/hifi_pll_clk
491515625       +/-15625Hz
* devmem 0xfe008100 32
0xD00304A3
* devmem 0xfe008104 32
0x00014820

Based on the register information read above, it can be obtained:
m = 0xA3 = 0d163;
n = 0x1 = 0d1
frac = 0x14820 = 0d84000
od = 0x3 = 0d3

hifi_pll calculates the output frequency:
calc_rate = xtal_rate / n * (m + (frac / frac_max)) >> od;
calc_rate = 24000000 / 1 * (163 + (84000 / 100000)) >> 3;
calc_rate = 491520000

clk_rate, msr_rate, and calc_rate all match.

The test and calculation results of S4 are consistent with those of C3,
which will not be repeated here.

Signed-off-by: Chuan Liu <chuan.liu@xxxxxxxxxxx>
---
Chuan Liu (4):
      clk: meson: Support PLL with fixed fractional denominators
      clk: meson: c3: pll: hifi_pll frequency is not accurate
      clk: meson: s4: pll: hifi_pll support fractional multiplier
      clk: meson: s4: pll: hifi_pll frequency is not accurate

 drivers/clk/meson/c3-pll.c  |  1 +
 drivers/clk/meson/clk-pll.c | 22 +++++++++++++++++++---
 drivers/clk/meson/clk-pll.h |  1 +
 drivers/clk/meson/s4-pll.c  |  9 +++++++--
 4 files changed, 28 insertions(+), 5 deletions(-)
---
base-commit: adac147c6a32e2919cb04555387e12e738991a19
change-id: 20240904-fix_clk-668f7a1a2b16

Best regards,
-- 
Chuan Liu <chuan.liu@xxxxxxxxxxx>