Re: [PATCH 1/4] clk: meson: Support PLL with fixed fractional denominators

[Chuan Liu]

On 2024/9/6 14:51, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Fri 06 Sep 2024 at 13:52, Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@xxxxxxxxxx> wrote:
>
> > From: Chuan Liu <chuan.liu@xxxxxxxxxxx>
> >
> > Some PLLs with fractional multipliers have fractional denominators that
> > are fixed to "100000" instead of the previous "(1 << pll->frac.width)".
> >
> > Signed-off-by: Chuan Liu <chuan.liu@xxxxxxxxxxx>
> > ---
> >   drivers/clk/meson/clk-pll.c | 22 +++++++++++++++++++---
> >   drivers/clk/meson/clk-pll.h |  1 +
> >   2 files changed, 20 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
> > index bc570a2ff3a3..f0009c174564 100644
> > --- a/drivers/clk/meson/clk-pll.c
> > +++ b/drivers/clk/meson/clk-pll.c
> > @@ -36,6 +36,12 @@
> >   #include "clk-regmap.h"
> >   #include "clk-pll.h"
> >
> > +/*
> > + * Some PLLs with fractional multipliers have fractional denominators that
> > + * are fixed to "100000" instead of the previous "(1 << pll->frac.width)".
> > + */
> > +#define FIXED_FRAC_MAX                       100000
> When the next arbitrary limit comes around, this will get very ugly.
> Instead, please add frac_max to the pll parameter


I also had this consideration before, and after confirmation, the
hifi_pll of the subsequent chip design will continue to be this value,
and the hifi_pll of the chip in recent years is also this value. So
let's define it here.

In the next version I replaced it with a member inside the structure
member of meson_clk_pll_data.


> > +
> >   static inline struct meson_clk_pll_data *
> >   meson_clk_pll_data(struct clk_regmap *clk)
> >   {
> > @@ -57,12 +63,17 @@ static unsigned long __pll_params_to_rate(unsigned long parent_rate,
> >                                          struct meson_clk_pll_data *pll)
> >   {
> >        u64 rate = (u64)parent_rate * m;
> > +     unsigned int frac_max;
> >
> >        if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
> >                u64 frac_rate = (u64)parent_rate * frac;
> >
> > -             rate += DIV_ROUND_UP_ULL(frac_rate,
> > -                                      (1 << pll->frac.width));
> > +             if (pll->flags & CLK_MESON_PLL_FIXED_FRAC_MAX)
> > +                     frac_max = FIXED_FRAC_MAX;
> > +             else
> > +                     frac_max = (1 << pll->frac.width);
> > +
> > +             rate += DIV_ROUND_UP_ULL(frac_rate, frac_max);
> >        }
> >
> >        return DIV_ROUND_UP_ULL(rate, n);
> > @@ -100,13 +111,18 @@ static unsigned int __pll_params_with_frac(unsigned long rate,
> >                                           unsigned int n,
> >                                           struct meson_clk_pll_data *pll)
> >   {
> > -     unsigned int frac_max = (1 << pll->frac.width);
> > +     unsigned int frac_max;
> >        u64 val = (u64)rate * n;
> >
> >        /* Bail out if we are already over the requested rate */
> >        if (rate < parent_rate * m / n)
> >                return 0;
> >
> > +     if (pll->flags & CLK_MESON_PLL_FIXED_FRAC_MAX)
> Certainly don't need a flag for that. Use a parameter and default to (1
> << pll->frac.width) if unset.
Okay
> > +             frac_max = FIXED_FRAC_MAX;
> > +     else
> > +             frac_max = (1 << pll->frac.width);
> > +
> >        if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST)
> >                val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate);
> >        else
> > diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h
> > index 7b6b87274073..e996d3727eb1 100644
> > --- a/drivers/clk/meson/clk-pll.h
> > +++ b/drivers/clk/meson/clk-pll.h
> > @@ -29,6 +29,7 @@ struct pll_mult_range {
> >
> >   #define CLK_MESON_PLL_ROUND_CLOSEST  BIT(0)
> >   #define CLK_MESON_PLL_NOINIT_ENABLED BIT(1)
> > +#define CLK_MESON_PLL_FIXED_FRAC_MAX BIT(2)
> Remove this.
>
> >   struct meson_clk_pll_data {
> >        struct parm en;
> --
> Jerome