[ EXTERNAL EMAIL ]
On Fri 06 Sep 2024 at 13:52, Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@xxxxxxxxxx> wrote:
From: Chuan Liu <chuan.liu@xxxxxxxxxxx>The patch title is not good. the clock innacurate ... Ok, but you are doing
something about it, right ? Plus just saying that is a bit vague.
How about something like "fix frac maximum value" ? This what you are
doing, right ?
The fractional denominator of C3's hifi_pll fractional multiplier is--
fixed to 100000, so flag CLK_MESON_PLL_FIXED_FRAC_MAX is added.
Fixes: 8a9a129dc565 ("clk: meson: c3: add support for the C3 SoC PLL clock")
Signed-off-by: Chuan Liu <chuan.liu@xxxxxxxxxxx>
---
drivers/clk/meson/c3-pll.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/meson/c3-pll.c b/drivers/clk/meson/c3-pll.c
index 32bd2ed9d304..a350173efe90 100644
--- a/drivers/clk/meson/c3-pll.c
+++ b/drivers/clk/meson/c3-pll.c
@@ -361,6 +361,7 @@ static struct clk_regmap hifi_pll_dco = {
.range = &c3_gp0_pll_mult_range,
.init_regs = c3_hifi_init_regs,
.init_count = ARRAY_SIZE(c3_hifi_init_regs),
+ .flags = CLK_MESON_PLL_FIXED_FRAC_MAX,
},
.hw.init = &(struct clk_init_data) {
.name = "hifi_pll_dco",
Jerome