Re: [PATCH v7 0/2] Add notifier for PLL0 clock and set it 1.5GHz on the JH7110 SoC

[Conor Dooley]

From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>

On Mon, 26 Aug 2024 16:04:28 +0800, Xingyu Wu wrote:
> This patch is to add the notifier for PLL0 clock and set the PLL0 rate
> to 1.5GHz to fix the lower rate of CPUfreq on the JH7110 SoC.
> 
> The first patch is to add the notifier for PLL0 clock. Setting the PLL0
> rate need the son clock (cpu_root) to switch its parent clock to OSC
> clock and switch it back after setting PLL0 rate. It need to use the
> cpu_root clock from SYSCRG and register the notifier in the SYSCRG
> driver.
> 
> [...]

Applied to riscv-soc-fixes, thanks!


[2/2] riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz
      https://git.kernel.org/conor/c/61f2e8a3a941

I applied this last night but forgot to send the ty email.