[PATCH 2/2] phy: freescale: fsl-samsung-hdmi: Add PLL LUT entries for some non-CEA-861 modes

[Frieder Schrempf]

In order to support some pixel clock values not specified in CEA-861
and not achievable by the integer PLL algorithm, we add some new LUT
entries. This allows to use the fractional-N PLL to achieve pixel
clocks of 75 MHz, 88.75 MHz and 296.703 MHz with high accuracy.

Signed-off-by: Frieder Schrempf <frieder@xxxxxxx>
---
 drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
index 401178bfcdda..6b36318630b2 100644
--- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
+++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
@@ -156,6 +156,9 @@ static const struct phy_config phy_pll_cfg[] = {
 	}, {
 		.pixclk = 74250000,
 		.pll_div_regs = { 0xd1, 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 },
+	}, {
+		.pixclk = 75000000,
+		.pll_div_regs = { 0xD1, 0x3E, 0x30, 0x9F, 0x0E, 0x82, 0x41 },
 	}, {
 		.pixclk = 78500000,
 		.pll_div_regs = { 0xd1, 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 },
@@ -165,6 +168,9 @@ static const struct phy_config phy_pll_cfg[] = {
 	}, {
 		.pixclk = 82500000,
 		.pll_div_regs = { 0xd1, 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 },
+	}, {
+		.pixclk = 88750000,
+		.pll_div_regs = { 0xD1, 0x6E, 0x50, 0x8B, 0x06, 0x81, 0x40 },
 	}, {
 		.pixclk = 89000000,
 		.pll_div_regs = { 0xd1, 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 },
@@ -277,6 +283,9 @@ static const struct phy_config phy_pll_cfg[] = {
 		.pixclk = 277500000,
 		.pll_div_regs = { 0xd1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d },
 	},  {
+		.pixclk = 296703000,
+		.pll_div_regs = { 0xd1, 0x7b, 0x18, 0xe0, 0x3d, 0x8a, 0x41 },
+	}, {
 		.pixclk = 297000000,
 		.pll_div_regs = { 0xd1, 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 },
 	},
-- 
2.46.0