[PATCH v3 3/8] arm64: dts: mediatek: mt8188: Add CPU performance controller for CPUFreq

From: Fei Shao
Date: Wed Sep 11 2024 - 10:36:15 EST


Add performance controller node and performance-domains properties for
CPUFreq support on MT8188 SoC.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
Signed-off-by: Fei Shao <fshao@xxxxxxxxxxxx>
---

(no changes since v1)

arch/arm64/boot/dts/mediatek/mt8188.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index cd27966d2e3c..cdd2fe14effa 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -41,6 +41,7 @@ cpu0: cpu@0 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
#cooling-cells = <2>;
};

@@ -59,6 +60,7 @@ cpu1: cpu@100 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
#cooling-cells = <2>;
};

@@ -77,6 +79,7 @@ cpu2: cpu@200 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
#cooling-cells = <2>;
};

@@ -95,6 +98,7 @@ cpu3: cpu@300 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
#cooling-cells = <2>;
};

@@ -113,6 +117,7 @@ cpu4: cpu@400 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
#cooling-cells = <2>;
};

@@ -131,6 +136,7 @@ cpu5: cpu@500 {
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
#cooling-cells = <2>;
};

@@ -149,6 +155,7 @@ cpu6: cpu@600 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
#cooling-cells = <2>;
};

@@ -167,6 +174,7 @@ cpu7: cpu@700 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
#cooling-cells = <2>;
};

@@ -880,6 +888,12 @@ soc {
compatible = "simple-bus";
ranges;

+ performance: performance-controller@11bc10 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+ #performance-domain-cells = <1>;
+ };
+
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
--
2.46.0.598.g6f2099f65c-goog