RE: [PATCH net-next V2 4/5] net: lan743x: Implement phylink pcs

[Ronnie.Kunin]

> -----Original Message-----
> From: Andrew Lunn <andrew@xxxxxxx>
> Sent: Thursday, September 12, 2024 11:28 AM
> To: Raju Lakkaraju - I30499 <Raju.Lakkaraju@xxxxxxxxxxxxx>
> Cc: netdev@xxxxxxxxxxxxxxx; davem@xxxxxxxxxxxxx; edumazet@xxxxxxxxxx; kuba@xxxxxxxxxx;
> pabeni@xxxxxxxxxx; Bryan Whitehead - C21958 <Bryan.Whitehead@xxxxxxxxxxxxx>; UNGLinuxDriver
> <UNGLinuxDriver@xxxxxxxxxxxxx>; linux@xxxxxxxxxxxxxxx; maxime.chevallier@xxxxxxxxxxx;
> rdunlap@xxxxxxxxxxxxx; Steen Hegelund - M31857 <Steen.Hegelund@xxxxxxxxxxxxx>; Daniel Machon -
> M70577 <Daniel.Machon@xxxxxxxxxxxxx>; linux-kernel@xxxxxxxxxxxxxxx
> Subject: Re: [PATCH net-next V2 4/5] net: lan743x: Implement phylink pcs
> 
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> 
> > > Also, am i reading this correct. C22 transfers will go out a
> > > completely different bus to C45 transfers when there is an SFP?
> >
> > No. You are correct.
> > This LAN743x driver support following chips 1. LAN7430 - C22 only with
> > GMII/RGMII I/F 2. LAN7431 - C22 only with MII I/F
> 
> Fine, simple, not a problem.
> 
> > 3. PCI11010/PCI11414 - C45 with RGMII or SGMII/1000Base-X/2500Base-X
> >    If SFP enable, then XPCS's C45 PCS access
> >    If SGMII only enable, then SGMII (PCS) C45 access
> 
> Physically, there are two MDIO busses? There is an external MDIO bus with two pins along side the
> RGMII/SGMII pins? And internally, there is an MDIO bus to the PCS block?
> 
> Some designs do have only one bus, the internal PCS uses address X on the bus and you are simply not
> allowed to put an external device at that address.
> 
> But from my reading of the code, you have two MDIO busses, so you need two Linux MDIO busses.
> 
>         Andrew

Our PCI11x1x hardware has a single MDIO controller that gets used regardless of whether the chip interface is set to RGMII or to SGMII/BASE-X.
When we are using an SFP, the MDIO lines from our controller are not used / connected at all to the SFP.

Raju can probably explain this way better than me since the how all this interaction in the linux mdio/sfp/xpcs frameworks work honestly goes over my head. From what he told me even when we are not using our mdio controller lines, since there is indirect access to the PHY (the one inside of the SFP) via the I2C controller (which btw does not share any hardware pins with those used by the MDIO controller), he had to change the PHY management functions for that indirect access to be used when SFP is selected.

Ronnie