RE: [PATCH net-next V2 4/5] net: lan743x: Implement phylink pcs

[Ronnie.Kunin]

> -----Original Message-----
> From: Andrew Lunn <andrew@xxxxxxx>
> Sent: Thursday, September 12, 2024 12:13 PM
> To: Ronnie Kunin - C21729 <Ronnie.Kunin@xxxxxxxxxxxxx>
> Cc: Raju Lakkaraju - I30499 <Raju.Lakkaraju@xxxxxxxxxxxxx>; netdev@xxxxxxxxxxxxxxx;
> davem@xxxxxxxxxxxxx; edumazet@xxxxxxxxxx; kuba@xxxxxxxxxx; pabeni@xxxxxxxxxx; Bryan
> Whitehead - C21958 <Bryan.Whitehead@xxxxxxxxxxxxx>; UNGLinuxDriver
> <UNGLinuxDriver@xxxxxxxxxxxxx>; linux@xxxxxxxxxxxxxxx; maxime.chevallier@xxxxxxxxxxx;
> rdunlap@xxxxxxxxxxxxx; Steen Hegelund - M31857 <Steen.Hegelund@xxxxxxxxxxxxx>; Daniel Machon -
> M70577 <Daniel.Machon@xxxxxxxxxxxxx>; linux-kernel@xxxxxxxxxxxxxxx
> Subject: Re: [PATCH net-next V2 4/5] net: lan743x: Implement phylink pcs
> 
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> > Our PCI11x1x hardware has a single MDIO controller that gets used
> > regardless of whether the chip interface is set to RGMII or to
> > SGMII/BASE-X.
> 
> That would be the external MDIO bus.
> 
> But where is the PCS connected?

For SGMII/BASE-X support the PCI11010 uses Synopsys IP which is all internal to the device. The registers of this Synopsys block are accessible indirectly using a couple of registers (called SGMII_ACCESS and SGMII_DATA) that are mapped into the PCI11010 PCIe BAR.

> 
> > When we are using an SFP, the MDIO lines from our controller are not
> > used / connected at all to the SFP.
> 
> Correct. The SFP cage does not have MDIO pins. There are two commonly used protocols for MDIO over
> I2C, which phylink supports. The MAC driver is not involved. All it needs to report to phylink is when the
> PCS transitions up/down.
> 
>     Andrew