Re: [PATCH 6.6 v2 1/4] riscv: dts: starfive: add assigned-clock* to limit frquency

[Christophe JAILLET]

Le 12/09/2024 à 04:55, WangYuli a écrit :
> From: William Qiu <william.qiu@xxxxxxxxxxxxxxxx>
>
> [ Upstream commit af571133f7ae028ec9b5fdab78f483af13bf28d3 ]
>
> In JH7110 SoC, we need to go by-pass mode, so we need add the
> assigned-clock* properties to limit clock frquency.
>
> Signed-off-by: William Qiu <william.qiu@xxxxxxxxxxxxxxxx>
> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>
> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> Signed-off-by: WangYuli <wangyuli@xxxxxxxxxxxxx>
> ---

Hi,

if/when resent, there is a typo in the subject: s/frquency/frequency/

CJ


>   .../riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index 062b97c6e7df..4874e3bb42ab 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -204,6 +204,8 @@ &i2c6 {
>   
>   &mmc0 {
>   	max-frequency = <100000000>;
> +	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
> +	assigned-clock-rates = <50000000>;
>   	bus-width = <8>;
>   	cap-mmc-highspeed;
>   	mmc-ddr-1_8v;
> @@ -220,6 +222,8 @@ &mmc0 {
>   
>   &mmc1 {
>   	max-frequency = <100000000>;
> +	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
> +	assigned-clock-rates = <50000000>;
>   	bus-width = <4>;
>   	no-sdio;
>   	no-mmc;