[PATCH v4 0/6] iommu/amd: Use 128-bit cmpxchg operation to update DTE

From: Suravee Suthikulpanit
Date: Mon Sep 16 2024 - 13:20:24 EST


This series modifies current implementation to use 128-bit cmpxchg to
update DTE when needed as specified in the AMD I/O Virtualization
Techonology (IOMMU) Specification.

Please note that I have verified with the hardware designer, and they have
confirmed that the IOMMU hardware has always been implemented with 256-bit
read. The next revision of the IOMMU spec will be updated to correctly
describe this part. Therefore, I have updated the implementation to avoid
unnecessary flushing.

Changes in v4:
* Patch 1: Update commit message
* Patch 2:
- Move get_dte256, clone_alias, dump_dte to patch 4
- Introduce write_upper, write_lower
- Introduce iommu_flush_sync_dte
- Reimplement update_dte256
* Patch 3: Remove spinlock since it is moved inside update_dte256()
* Patch 4: Update clone_alias() and dump_dte()
* Patch 5: Update clear_dte_entry()

v3: https://lore.kernel.org/lkml/20240906121308.5013-1-suravee.suthikulpanit@xxxxxxx/
v2: https://lore.kernel.org/lkml/20240829180726.5022-1-suravee.suthikulpanit@xxxxxxx/
v1: https://lore.kernel.org/lkml/20240819161839.4657-1-suravee.suthikulpanit@xxxxxxx/

Thanks,
Suravee

Suravee Suthikulpanit (6):
iommu/amd: Disable AMD IOMMU if CMPXCHG16B feature is not supported
iommu/amd: Introduce helper function to update 256-bit DTE
iommu/amd: Modify set_dte_entry() to use 256-bit DTE helpers
iommu/amd: Introduce helper function get_dte256()
iommu/amd: Modify clear_dte_entry() to avoid in-place update
iommu/amd: Lock DTE before updating the entry with WRITE_ONCE()

drivers/iommu/amd/amd_iommu.h | 2 +
drivers/iommu/amd/amd_iommu_types.h | 10 +-
drivers/iommu/amd/init.c | 23 +-
drivers/iommu/amd/iommu.c | 332 ++++++++++++++++++++--------
4 files changed, 265 insertions(+), 102 deletions(-)

--
2.34.1